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AP160 8-BIT MICROCONTROLLER WITH 8KB OTP
GENERAL DESCRIPTION
The AP160 is a wide operating voltage, Low power consumption and high performance with AMIC high-density CMOS technology. All instruction set of AP160 are fully compatible with the standard 8051. The AP160 contains 8K bytes OTP EPROM, 256 bytes RAM, four 8-bit bi-directional and bit addressable I/O ports, three 16-bit timer/counter and eight interrupt sources. To reduce power consumption, idle mode and power down mode are provided to implementation. For data protection, program lock bits can be performed through programming LB1, LB2 and LB3. The AMIC AP160 is a useful and powerful microcontroller in many control system application.
DATA SHEET
October 2001
FEATURES
l l l l l l l l l l l l l
Compatible with MCS-51 Products 256 X 8 bit internal Data RAM. 8KB On-Chip OTP EPROM. 2.7V~5.5V Operating Range. Fully Static Operation : 0Hz to 16 MHz 0~33MHZ speed range at VCC=5V. 32 Programmable I/O pins Three 16-Bit Timers/Counters. Programmable clock out. Full-duplex UART Eight interrupt sources. 2 level priority-interrupt. Power reduction control modes
n n
Idle mode Power-down mode
l l l l
3 security bits. Low EMI (Inhibit ALE) Wake-up from Power Down by an external interrupt. Available in PLCC and QFP44 packages.
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PIN CONFIGURATIONS
n PLCC
P1.1 (T2EX)
P0.0 (AD0)
P0.1 (AD1) 42
P0.2 (AD2) 41
6
5
4
3
2
1
44
43
40 39 38 37 36 35 34 33 32 31 30 29
P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
P0.3 (AD3)
P1.0 (T2)
NC VCC
P1.4
P1.3
P1.2
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
AP160L
(WR) P3.6
(RD) P3.7 XTAL2
XTAL1
GND NC
(A8) P2.0
(A9) P2.1 P0.0 (AD0)
(A10) P2.2 P0.1 (AD1) 36
n QFP
P1.1 (T2EX)
P0.2 (AD2) 35
44
43
42
41
40
39
38
37
P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
1 2 3
34 33 32 31
P0.3 (AD3)
P1.0 (T2)
NC VCC
P1.4
P1.3
P1.2
(A11) P2.3 (A12) P2.4
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
AP160F
4 5 6 7 8 9 10 11 12 13 14 15 16
30 29 28 27 26 25 24 23
17
18
19
20 (A10) P2.2
21
(WR) P3.6
(RD) P3.7 XTAL2
XTAL1
GND GND
(A8) P2.0
(A9) P2.1
(A11) P2.3 (A12) P2.4
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BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
VCC PORT 0 DRIVERS GND PORT 2 DRIVERS
RAM ADDR. REGISTER
RAM
PORT0 LATACH
PORT2 LATACH
QUICK FLASH
B REGISTER
ACC
STACK POINTER
PROGRAM ADDRESS REGISTER
TMP2
TMP1
BUFFER
ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW
PC INCREMENTER
PROGRAM COUNER
PSEN
ALE/ PROG EA /VPP RST
TIMING AND CONTROL
INSTRUCTION REGISTER
DPTR
PORT1 LATACH
PORT3 LATACH
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0-P1.7
P3.0-P3.7
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PIN DESCRIPTIONS
SYMBOL VSS VCC P0.0-P0.7 TYPE I I I/O Ground. Supply voltage. Port 0 is an 8-bit open drain, bidirectional I/O port. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during programming on-chip OTP EPROM and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current ( IIL ) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following: T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out) T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control. Port 1 also receives the low-order address bytes during programming on-chip OTP EPROM and verification. P2.0-P2.7 I/O Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current ( IIL ) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during programming on-chip OTP EPROM and verification. Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current ( IIL ) because of the pullups. Port 3 also serves the functions of various special features of the AP160, as shown below: RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port 3 also receives some control signals for programming and verification. RST I Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. DESCRIPTIONS
P1.0-P1.7
I/O
P3.0-P3.7
I/O
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SYMBOL ALE/PROG TYPE O/I DESCRIPTIONS Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Programming on-chip OPT EPROM. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. Program Store Enable is the read strobe to external program memory. When the AP160 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during programming OTP EPROM. Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier.
PSEN
O
EA/Vpp
I
XTAL1 XTAL2
I O
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SPECIAL FUNCTION REGISTERS
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Table 1. AP160 SFR Map and Reset Values 0F8H 0FFH
0F0H
B 00000000
0F7H
0E8H
0EFH
0E0H
ACC 00000000
0E7H
0D8H
0DFH
0D0H
PSW 00000000 T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00000000 TL2 00000000 TH2 00000000
0D7H
0C8H
0CFH
0C0H
0C7H
0B8H
IP XX000000 P3 11111111 IE 0X000000 P2 11111111 SCON 00000000 P1 11111111 TCON 00000000 P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 TH0 00000000 TH1 00000000 PCON 0XXX0000 SBUF XXXXXXXX
0BFH
0B0H
0B7H
0A8H
0AFH
0A0H
0A7H
098H
09FH
090H
097H
088H
08FH
080H
087H
Note that not all of the addresses are occupied. Unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future AMIC products to invoke new features. In that case the reset or inactive values of the new bits will always be 0.
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TIMER2
Timer2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Table 2. T2CON - Timer/Counter 2 Control Register T2CON Address = 0C8H Bit 7 6 5 TF2 EXF2 RCLK Reset Value = 00000000 Bit Addressable Symbol TF2 EXF2
4 TCLK
3 EXEN2
2 TR2
1 C/T2
0 CP/RL2
RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Function Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN=1). Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock. Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/Stop control for Timer 2. TR2 = 1 starts the timer. Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered0. Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/Rl2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
Table 3. Timer 2 Operating Modes RCLK+TCLK 0 0 1 X
CP/RL2 0 1 X X
TR2 1 1 1 0
MODE 16-Bit Auto-Reload 16-Bit Capture Baud Rate Generator (Off)
Timer2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
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Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2=1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 1.
OSC
/ 12
C/T2=0
TH2 CONTROL TR2
TL2
TF2 OVERFLOW
C/T2=1 T2 PIN TRANSITION DETECTOR T2EX PIN
CAPTURE
RCAP2H
RCAP2L TIMER 2 INTERRUPT
EXF2 CONTROL EXEN2
Figure 1. Timer in Capture Mode
Auto-Reload (UP or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 3). Upon reset, the DCEN bit is set to 0 so that Timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Figure 2 shows Timer 2 automatically counting up when DCEN=0.
OSC
/ 12
C/T2=0
TH2 CONTROL TR2 C/T2=1 RELOAD T2 PIN RCAP2H TRANSITION DETECTOR T2EX PIN CONTROL EXEN2
TL2 OVERFLOW
RCAP2L TF2 EXF2
TIMER 2 INTERRUPT
Figure 2. Timer 2 Auto Reload Mode (DCEN=0)
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In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2=0, Timer2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture Mode RCAP2H and RCAP2L are preset by software. If EXEN2=1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer2 to count up or down, as shown in Figure 3. In the mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. The overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and Tl2 equal the values stored in RCAP2H and RACP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles th whenever Timer 2 overflows or underflows and can be used as a 17 bit of resolution. In this operating mode, EXF2 does not flag an interrupt. Table 3. T2MOD (Timer 2 Mode Control Register) T2Mod Address = 0C9H Not bit addressable Bit 7 Symbol Symbol T2OE DCEN
Reset Value = XXXX XX00B
6 -
5 -
4 -
3 -
2 -
1 T2OE
0 DCEN
Function Not implemented, reserved for future Timer 2 Output Enable bit. When set, this bit allows Timer 2 to be configured as an up/down counter.
(DOWN COUNTING RELOAD VALUE) 0FFH 0FFH
TOGGLE EXF2
OVERFLOW OSC
/ 12
C/T2=0
TH2 CONTROL TR2 C/T2=1 T2 PIN RCAP2H
TL2
TF2
TIMER 2 INTERRUPT RCAP2L COUNT DIRECTION 1=UP 0=DOWN T2EX PIN
(UP COUNTING RELOAD VALUE)
Figure 3. Timer 2 Auto Reload Mode (DCEN=1)
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Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in Th2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate according to the following equation.
Mode 1 and 3 Baud Rates =
Timer 2 Overflow Rate 16
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2=0). The Timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
Modes 1 and 3 Oscillator Frequency = Baud Rate 32 x [65536 - ( RCAP 2 H , RCAP 2 L)]
where (RCAP2H,RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK=1 in T2CON. Note that a rollover in TH2 does not ser TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Thus when timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2=1) as a timer in the baud rate generator mode. TH2 or TL2 should not be read from or written to. Under there conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the timer 2 or RCAP2 register.
TIMER 1 OVERFLOW
NOTE:OSC FREQ. IS DIVIDED BY 2, NOT 12
/
2
"0" "1" SMOD1 "1" "0" RCLK
/ 16
OSC
/
2
C/T2=0
TH2 CONTROL TR2 C/T2=1 T2 PIN TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 EXF2 RCAP2H
TL2
RX CLOCK
"1"
"0" TCLK TX CLOCK
RCAP2L
/ 16
TIMER 2 INTERRUPT
Figure 4. Timer 2 in Baud Rate Generator Mode
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Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 HZ to 4MHZ at a 16MHZ operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit Tr2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.
Clock - Out Frequency =
Oscillator Frequency 4 x [65535 - ( RCAP 2 H , RCAP 2 L)]
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.
TL2 (8 BITS) TH2 (8 BITS)
OSC
/2
TR2
RCAP2L C/T2 BIT
RCAP2H
P1.0 (T2)
/2
TRANSITION DETECTOR
T2OE (T2MOD.1)
P1.1 (T2EX)
EXF2
TIMER 2 INTERRUPT
EXEN2
Figure 5. Timer 2 in Clock-Out Mode
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INTERRUPTS
The AP160 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 4 shows that bit position IE.6 is unimplemented. User software should not write 1s to the bit position, since they may be used in future AMIC products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows. Table 4: Interrupt Enable (IE) Register (MSB) EA -ET2 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. Function Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. -IE.6 Reserved. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. User software should never write 1s to unimplemented bits, because they may be used in future AMIC products Symbol EA Position IE.7
ES
ET1
EX1
ET0
(LSB) EX0
0 INT0 1 IE0
TF0
0 INT1 1 IE1
TF1 T1 R1 TF2 EXF2
Figure 6. Interrupt Sources
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DATA MEMORY
The AP160 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail-able as stack space.
POWER MANAGEMENT IDLE MODE
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.
POWER DOWN MODE
In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The way to exit from power down mode is either hardware reset or external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Status of External Pins During Idle and Power Down Modes
Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles.
REDUCED EMI
All port pins of the AP160 have slew rate controlled outputs. This is to limit noise generated by quickly switching output signals. The slew rate is factory set to approximately 10 ns rise and fall times. AUXR Address = 8EH Bit 7 6 5 4 3 NOTE: The AO bit (AUXR.0) in the AUXR register when set disables the ALE output. 2 1 0 AO
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EPROM PROGRAMMING MODE
The setup for programming and verification on-chip OPT EPROM of AP160 is shown in Figure 7 and Figure 8, independently. The address of the EPROM location to be programmed is applied to ports 1 and 2. The code byte to be programmed into that location and read verified data are applied to port 0. The programming, verifying, Write Lock bits and read signature byte mode are selectable by the pins of RST, PSEN, ALE/PROG, P2.6, P2.7, P3.6 and P3.7, as shown in table 8. The programming and verification waveform is shown in Figure 9. VCC must be rising to VCC1 during programming.
VCC1 VCC1
A0~A7 ADDR 0000H/1FFFH A8~A12
P1 P2.0~P2.4
VCC P0 PGM DATA
A0~A7 ADDR 0000H/1FFFH A8~A12
P1 P2.0~P2.4
VCC P0 PGM DATA (10K PULLUPS)
P2.6 P2.7 P3.6 P3.7 ALE PROG
P2.6 P2.7 P3.6 P3.7 VIH ALE
SEE TABLE 8.
SEE TABLE 8.
XTAL2
EA
VIH/VPP
XTAL2
EA
XTAL1 GND
RST PSEN
VIH
XTAL1 GND
RST PSEN
VIH
Figure 7. Programming the EPROM MEMORY
Figure 8. Verifying the EPROM MEMORY.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Symbol VPP VCC1 IPP t AS t DS t VPS t VCS t PW t DH t VR t DV t DFP t AH Parameter Programming Voltage Programming Supply Voltage VPP Current During Program Address Valid to Program Low Input Valid to Program Low VPP Setup Time VCC Setup Time Program Pulse Width Data Hold Time EA/VPP Recovery Time Data Valid from P2.7 Chip Enable to Output Float Delay Address Hold Time 0 Min. 11.5 6.0 2 2 2 2 95 2 2 100 130 105 Max. 12.5 6.5 1.0 Unit V V mA us us us us us us us ns ns ns Test Conditions
ALE/PROG = VIL
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PRGRAMMING AND VERIFY MODE AC WAVEFORMS
PROGRAM VERIFY
ADDRESS (P1.0~P1.7 P2.0~P2.4)
VIH VALID VIL tAS
DATA (PORT 0)
tDS
DATA IN
Hi-Z tDV tDH VPP LOGIC 1 LOGIC 0
DATA OUT tDFP
VCC
EA/VPP
tVPS VCC1 tVPS
VCC
VCC
tVCS tPW
ALE/PROG
tVR tAH
P2.7
Table 8. EPROM PROGRAMMING MODE Mode RST Write Code Data Read Code Data Bit -1 Write Lock Bit -2 Bit -3 Read Signature Byte H H H H H H
PSEN L L L L L L
ALE/PROG EA/VPP 12V H H 12V 12V 12V H H
P2.6 L L H H H L
P2.7 H L H H L L
P3.6 H H H L H L
P3.7 H H H L L L
Note: The signature bytes are read by the same procedure as a normal verification of locations 30H, 31H and 32H. The values returns are as follows: (30H) = 37H indicates manufactured by AMIC. (31H) = 6EH indicates embedded OTP device. (32H) = 7FH indicates JEDEC continuation code.
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PROGRAM MEMORY LOCK BITS
The AP160 has three lock bits that can be left unprogrammed(U) or can be programmed (P) to obtain the additional features listed in the following table. Program Lock Bits LB1 U P LB2 U U Protection Type LB3 U No program lock features U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the OPT EPROM is disabled. U Same as mode 2, but verify is also disabled. P Same as mode 3, bur external execution is also disabled.
1 2
3 4
P P
P P
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
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ABSOLUTE MAXIMUM RATINGS
Parameter Operating temperature under bias Storage temperature range Voltage on EA/V PP pin to V SS Voltage on any other pin to V SS Maximum Operating Voltage Maximum I OL per I/O pin Rating -55 to +125 -65 to +150 0 to +12.5 -0.1 to +7.0 6.0 15.0 Unit C C V V V mA
NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC CHARACTERICSTICS
The values shown in this table are valid for T A = -40C to 85C and V CC = 2.7V to 5.5V, unless otherwise noted. Parameter Condition Min Max Units Symbol Input Low Voltage (Except EA) -0.5 0.2 VCC-0.1 V VIL VIL1 VIH VIH1 VOL VOL1 VOH Input Low Voltage (EA) Input High Voltage Input High Voltage Output Low Voltage (Ports 1,2,3) Output Low Voltage (Port 0, ALE, PSEN) Output High Voltage (Port 1,2,3, ALE, PSEN) (Except XTAL1, RST) (XTAL1, RST) I OL = 1.6mA I OL = 3.2mA IOH =-60uA, VCC=5V10% IOH =-25uA IOH =-10uA VOH1 Output High Voltage (Port 0 in External Bus Mode) IOH =-800uA, VCC=5V10% IOH =-300uA IOH =-80uA IIL ITL ILI RRST C IO Logical 0 Input Current (Ports 1,2,3) Logical 1 to 0 Transition Current (Ports 1,2,3) Input Leakage Current (Port 0, EA) Reset Pulldown Resistor Pin Capacitance Power Supply Current VIN =0.45V VIN =2V, VCC=5V10% 0.45< VIN < VCC 50 Test Freq. =1 MHZ, TA =25 C 2.4 0.75 VCC 0.9 VCC 2.4 0.75 VCC 0.9 VCC -50 -650 10 300 10 25 6.5 100 40 -0.5 0.2 VCC+0.9 0.7 VCC 0.2 VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45 V V V V V V V V V V V uA uA uA K PF mA mA uA uA
Active Mode, 12 MHZ Idle Mode, 12MHZ Power Down Mode VCC = 5.5V VCC = 3V Notes: 1. Under steady state (non-transient) conditions, I OL must be externally limited as follows: ICC Maximum I OL per port pin: 10mA Maximum I OL per 8-biit port: Port 0: 26mA, Ports 1,2,3: 15mA Maximum total I OL for all output pins: 71mA
If I OL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink currenr greater than the listed test condition. 2. Minimum VCC for Power Down is 2V.
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AC CHARACTERISTICS
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol 1/t CLCL t LHLL t AVLL t LLAX t LLIV t LLPL t PLPH t PLIV t PXIX t PXIZ t PXAV t AVIV t PLAZ t RLRH t WLWH t RLDV t RHDX t RHDZ t LLDV t AVDV t LLWL t AVWL t QVWX t QVWH t WHQX t RLAZ t WHLH Parameter Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address to RD or WR Low Data Valid to WR Transition Data Valid to WR High Data Hold After WR RD low to Address Float RD or WR High to ALE High 43 200 203 33 433 33 0 123 t CLCL -40 0 97 517 585 300 3 t CLCL -50 4 t CLCL -130 t CLCL -50 7 t CLCL -150 t CLCL -50 0 t CLCL +40 400 400 252 0 2 t CLCL -70 8 t CLCL -150 9 t CLCL -165 3 t CLCL +50 75 312 10 6 t CLCL -100 6 t CLCL -100 5 t CLCL -165 0 59 t CLCL -8 5 t CLCL -105 10 43 205 145 0 t CLCL -25 127 43 48 233 t CLCL -40 3 t CLCL -45 3 t CLCL -105 12MHZ Oscillator Min Max Variable Oscillator Min Max 0 16 2 t CLCL -40 t CLCL -40 t CLCL -35 4 t CLCL -100 Units MHZ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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External Program Memory Read Cycle
tLHLL
ALE
tPLPH tAVLL tLLPL tLLIV tPLIV tPXAV tPLAZ tLLAX tPXIZ tPXIX INSTR IN tAVIV A0-A7
PSEN
PORT 0
A0-A7
PORT 2
A8-A15
A8-A15
External Data Memory Read Cycle
tLHLL
ALE
tWHLH tLLDV
PSEN
tLLWL
tRLRH
RD
tAVLL
tLLAX tRLDV tRLAZ tRHDX DATA IN tRHDZ
PORT 0
A0-A7 FROM RI OR DPL
tAVWL tAVDV
A0-A7 FROM PCL
INSTR IN
PORT 2
P2.0-P2.7 OR A8-A15 FORM DPH
A8-A15 FROM PCH
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EXTERNAL CLOCK DRIVE WAVEFORMS
tCHCX tCHCX tCLCH tCHCL
VCC-0.5V 0.7 VCC
0.2 VCC-0.1V 0.45V
tCLCX tCLCL
EXTERNAL CLOCK DRIVE
Symbol 1/ t CLCL t CLCL t CHCX t CLCX t CLCH t CHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall time Min 0 62.5 20 20 20 20 Max 16 Units MHZ ns ns ns ns ns
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SERIAL PORT TIMING: SHIFT REGISTER MODE TEST CONDITIONS
The values in this table are valid for VCC = 2.7V to 5.5V and Load Capacitance = 80pF Symbol Parameter 12MHZ Osc Variable Oscillator Min Max Min Max Serial Port Clock Cycle Time 1.0 12 t CLCL t XLXL t QVXH t XHQX t XHDX t XHDV Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 700 50 0 700 10 t CLCL -133 2 t CLCL -117 0 10 t CLCL -133 Units ns ns ns ns ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION ALE
tXLXL
0 1 2 3 4 5 6 7 8
CLOCK
tQVXH tXHQX 1 tXHDV
VALID VALID
WRITE TO SBUF OUTPUT DATA CLEAR RI INPUT DATA
0
2 tXHDX
3
4
5
6
7
SET TI
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
AC TESTING INPUT/OUTPUT WAVEFORMS
VCC-0.5V 0.2 VCC + 0.9V TEST POINTS 0.2 VCC - 0.1V 0.45V
Note: 1. AC Inputs during testing are driven at V CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V IH min. for a logic 1 and V IL max. for a logic 0.
FLOAT WAVEFORMS
VLOAD + 0.1V VLOAD VLOAD - 0.1V TIMING REFERENCE POINTS VOL + 0.1V VOL - 0.1V
Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH /VOL level occurs.
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ORDERING INFORMATION
Part Number AP160L AP160F Package Type PLCC QFP Operation Temperature Range -40 C ~ +85 C -40 C ~ +85 C
NOTE : AMIC Technology, Inc. reserves the right to make changes without prior notice.
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Package Information PLCC 44L Outline Dimension
HD D 6 1 44 40 39 0.630/0.590
unit: inches/mm
7
17 18 28
29
HE
E
0.014/0.0008 C
0.150 REF
L
A2
e
0.050 REF Seating Plane GD 0.630/0.590
b 0.022/0.016 b1 0.032/0.026
A1 D 0.020 MIN
A
0.004
y
Dimensions in inches Symbol A D E HD HE L
Dimensions in mm Min 16.46 16.46 17.27 17.27 2.29 0 Nom 16.59 16.59 17.53 17.53 2.54 Max 4.70 16.71 16.71 17.78 17.78 2.79 10
Min 0.648 0.648 0.680 0.680 0.090 0
Nom 0.653 0.653 0.690 0.690 0.100 -
Max 0.185 0.658 0.658 0.700 0.700 0.110 10
Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only.
GE
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Package Information QFP 44L Outline Dimensions
D D1 44 34 See Detail A
unit: inches/mm
1
33
E1 11 23 12 22
E
0.20 min 0 min C 0.25
A2
A
A1
e
b
0.10 D
Gauge Plane Seating Plane L 1.6
DETAIL A
Symbol A A1 A2 b D D1 E E1 L e C
Dimensions in inches Min 0.010 0.0748 0.5118 0.3897 0.5118 0.3897 0.0287 0.0021 0 Nom 0.012 0.0787 0.012 TYP 0.5196 0.3937 0.5196 0.3937 0.0346 0.0315 TYP 0.0060 0.0099 7 0.5274 0.3977 0.5275 0.3977 0.0366 Max 0.106 0.014 0.0866
Dimensions in mm Min 0.25 1.9 13.00 9.9 13.00 9.9 0.73 0.1 0 Nom 0.30 2.0 0.3 TYP 13.20 10.00 13.20 10.00 0.88 0.80 TYP 0.15 0.2 7 13.40 10.10 13.40 10.10 0.93 Max 2.7 0.35 2.2
Notes: 1. Dimensions D1 and E1 do not include mold protrusion. 2. Dimension b does not include dambar protrusion.
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Corporation Headquarters
6F, No. 5, Li-Shin Road VI, Hsin Chu, HSIP, Taiwan, R.O.C. Tel : 886-3-567-9966 Fax : 886-3-567-9977 Web : www.amic.com.tw
ASIA Pacific
AMIC Technology, Inc. 17F-8, No. 77, Shin Tai Wu Road, Shi Chi, Taipei, Taiwan, R.O.C. Tel : 886-2-2698-1131 Fax : 886-2-2698-1030
Europe
AMIC Technology (EUROPE) B.V. Crown Point Building, De Paal 1-6,13351 JA, P.O Box 50053,1305 AB, Almere, The Netherlands Tel. +31-36-5359666 Fax. +31-36-5401888
US and Canada
AMIC Technology Inc. 2518 Mission College Blvd., Suite 102 Santa Clara, CA 95054, U.S.A. Tel. +408-988-8818 Fax. +408-988-8817
Copyright (c) 2001 AMIC Technology, Inc. Specification subject to change without notice. All rights reserved.
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